This application relies for priority upon Korean Patent Application No. 2001-59041, filed on Sep. 24, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention generally relates to semiconductor integrated circuits. More particularly, the invention relates to a D flip-flop that is synchronized with a clock signal to have a memory function for storing an input signal or for outputting the stored signal.
In recent years, the development of information and communication technologies has had a great effect on society and culture. Particularly, the rapid advancement of the Internet technologies, personal terminals, and portable computers requires processing of a large amount of information. This has driven toward the successful development of microprocessors having a clock speed of greater than 1 GHz.
In view of the trend toward high integration and high speed systems, internal circuits constituting a high-speed digital system or a clock network must be carefully designed. The internal circuits of the high-speed digital system have at least two functions. The first is a logic function for transmitting a desired output signal in response to an input signal, and the second is a memory function for storing an input signal or outputting the stored signal in synchronization with a clock signal. Flip-flops are essential components in both functions, but especially in a circuit block having the memory function.
The most basic structure of the flip-flop is a master-slave structure having two JK latches that are coupled. However, this structure cannot be applied to a high-speed digital system because of its complexity and low operation speed. In order to overcome these disadvantages of the master-slave structure, dynamic type flip-flops using a parasitic capacitance of an internal node have been developed. Unfortunately, the dynamic type flip-flop requires two or more clock signals and is very sensitive to a racing problem generated by skew between the clock signals. In order to overcome these disadvantages of the dynamic type flip-flop, true single phase clocking (TSPC) D flip-flips have been proposed. The TSPC D flip-flop uses only one clock signal that is not absolutely inverted, and offers advantages such as a small area for clock lines, a reduced clock skew, and high speed operation. One example of the TSPC D flip-flop is disclosed in U.S. Pat. No. 6,060,927 entitled xe2x80x9cHIGH-SPEED D FLIP-FLOPxe2x80x9d, the content of which is incorporated herein by reference, in their entirety.
FIG. 1A is a circuit diagram of the TSPC D flip-flop illustrated in U.S. Pat. No. 6,060,927 and shows a technology to achieve a low power consumption and a high-speed response caused by an internal capacitance reduction. A flip-flop shown in FIG. 1A includes first to third latches. The first latch receives a clock signal CLK and a data signal D to generate a first output signal Q1xe2x80x2. The second latch receives the first output signal Q1xe2x80x2 and the clock signal CLK to generate a second output signal Q1xe2x80x3. The third latch receives the second output signal Q1xe2x80x3 and the clock signal CLK to generate a third output signal/Q1. The inverter 17 receives the third output signal/Q1 to generate a data signal Q1 at a rising or falling edge of the clock signal CLK. Preferably, the first and second latches are ratioed latches having serially coupled pull-up and pull-down elements. Preferably, the third latch is a clock operated latch.
Since static current always flows to the ratioed latch, the ratioed latch consumes a considerable amount of current. Also, since the voltage at each connecting node of the pull-up and pull-down elements does not fully swing, the ratioed latch is very sensitive to noise. Therefore, it is very difficult to design the ratioed latch. That is, in the ratioed latch, the pull-up elements must be designed to be 7-8 times larger than the pull-down elements.
Another example of the TSPC D flip-flop is disclosed in U.S. Pat. No. 5,592,114 entitled xe2x80x9cTRUE TYPE SINGLE-PHASE SHIFT CIRCUITxe2x80x9d, the content of which is incorporated herein by reference, in its entirety. FIG. 1B is a circuit diagram of the TSPC D flip-flop illustrated in the U.S. Pat. No. 5,592,114. A TSPC D flip-flop shown in FIG. 1B is a positive edge-triggered D flip-flop including four PMOS transistors MP0, MP1, MP2, and MP3, and five NMOS transistors MN0, MN1, MN2, MN3, and MN4. A gate of the PMOS transistor MP0 and a gate of the NMOS transistor MN0 are connected to a data signal D. Gates of the PMOS transistors MP1 and MP2 and gates of the NMOS transistors MN2 and MN3 are connected to a clock signal CLK. A drain of the PMOS transistor MP3 and a drain of the NMOS transistor MN3 are connected to an output terminal Qb. A gate of the NMOS transistor MN1 is connected to an A node, i.e., a common drain node A to which a drain of the PMOS transistor MN1 and a drain of the NMOS transistor MN0 are commonly connected. A gate of the PMOS transistor MP3 and a gate of the NMOS transistor MN4 are connected to a B node, i.e., a common drain node B to which a drain of he PMOS transistor MP2 and a drain of the NMOS transistor MN1 are commonly connected.
When the clock signal CLK is low (e.g., ground voltage) and a data signal D is low, the potential of the A node is made low or high (e.g., power supply voltage Vcc) according to the data signal D. Meanwhile, when the clock signal CLK is low and the data signal D is high, the potential of the A node is made low. In this case, the B node is precharged to a high level. When the B node is precharged, an output terminal Qb is to latch a previous output value. Therefore, the B node maintains the previous output value. When the clock signal CLK has a low-to-high transition, a potential of the B node is to be held at a previously precharged level or is to be made low. Therefore, a potential of the output terminal Qb is to be made low or high.
Limitations of the TSPC D flip-flop shown in FIG. 1B will now be described. The first limitation is that the flip-flop is very sensitive to a clock slope (rising or falling time of a clock signal). This will be explained in detail below. FIG. 2 shows output waveforms obtained when a clock slope is maintained at 0.3 ns in a clock frequency of 100 MHz. In FIG. 2, the region of the output terminal signal Qb enclosed in a dashed circle is ideally a period that must be maintained high. Nonetheless, the voltage level of the output terminal Qb is unstably maintained during this period.
This unstable period arises because the moment the data signal D is low and the clock signal CLK transitions high to low, charges of the output terminal Qb are discharged. That is, if the slope of the clock signal CLK is not quite vertical, there is a period where the NMOS transistors MN3 and MN4 are transitorily turned on at the same time. This allows the charges of the output terminal Qb to be discharged through the NMOS transistors MN3 and MN4. More specifically, when the potential of the B node transitions low to high and the clock signal transitions high to low, there is a period where the high levels overlap each other, as shown in FIG. 3. This allows the NMOS transistors MN3 and MN4 to be turned on at the same time. Consequently, the charges of the output terminal Qb are discharged through the turned-on transistors MN3 and MN4. The gentler the clock slope becomes, the more the overlap periods of the high level increase. In a worst case scenario, erroneous data may be transmitted. As a result, the TSPC D flip-flop shown in FIG. 1B is very sensitive to the clock slope.
A second limitation associated with the TSPC D flip-flop shown in FIG. 1B is that a glitch can occur. Whenever the data signal D is maintained low and the clock signal CLK transitions low to high, the glitch occurs in the output signal Qb, as illustrated in the region enclosed by the dotted line in FIG. 4. Ideally, the output signal Qb must be continuously maintained high while the data signal D is maintained low. However, when the clock signal CLK transitions high to low and the potential of the B node transitions high to low, a glitch phenomenon occurs where the output signal Qb is transitorily discharged and then recharged, as shown in FIG. 5. The glitch phenomenon occurs because the NMOS transistors MN3 and MN4 are transitorily turned on at the same time. Further, the glitch phenomenon causes the logic block of the next stage to consume additional power.
An approach for overcoming the aforementioned glitch phenomenon is disclosed by Q. Huang, xe2x80x9cSpeed Optimization Of Edge-Triggered CMOS Circuits For Gigahertz Single-Phase Clocksxe2x80x9d, IEEE Journal of Solid-State Circuits (Vol. 31, No. 3, pp. 456-465, March, 1996). However, this approach requires as many as 12 transistors, and therefore does not led itself well to high integration.
A third limitation is that the flip-flop shown in FIG. 1B has an asymmetric propagation delay time. Ideally, the TSPC D flip-flop is to have equivalent high-to-low and low-to-high propagation delay times, for advantageous power consumption and speed of the TSPC D flip-flop. In the case where the output signal Qb transitions high to low, the TSPC D flip-flop operates at very high speed; whereas, in the case where the output signal Qb transitions low to high, the TSPC D flip-flop operates at very low speed. That is, as the B node is discharged to low level, the output signal Qb is charged to high level, as shown in FIG. 6B. Such a path is more complex, as compared to a transition path of FIG. 6A. Therefore, the TSPC D flip-flop of FIG. 1B has different high-to-low and low-to-high propagation delay times. Solid lines of FIG. 6A and FIG. 6B represent signal transmission paths, respectively.
In conclusion, the TSPC D flip-flops described above are limited in that they are sensitive to the slope of a clock signal, and in that a glitch phenomenon is generated. Thus, there is a demand for a TSPC D flip-flop of a novel structure that prevents the output signal from being transitorily discharged at an undesirable time.
A first feature of the present invention is to provide a high-speed D flip-flop that prevents an output signal from being transitorily discharged at an undesirable time.
Another feature of the present invention is to provide a high-speed D flip-flop that prevents a glitch phenomenon in the output signal.
Still another feature of the present invention is to provide a high-speed D flip-flop that reduces setup time.
Still another feature of the present invention is to provide a high-speed D flip-flop that secures equivalent low-to-high and high-to-low transition times of the output signal.
In order to achieve these features, the present invention provides a high-speed discharge-suppressed D flip-flop as a data storage device. The flip-flop includes first to third nodes and a first precharge means for precharging the first and second nodes to a first supply voltage in response to a clock signal. The first switching means provides a first discharge path between the first and third nodes in response to an input signal. The second switching means provides a second discharge path between the second and third nodes in response to a potential of the first node. The second precharge means precharges an output terminal to the first supply voltage in response to a potential of the second node. The third switching means provides a third discharge path between the output terminal and the third node in response to the potential of the second node. The fourth switching means connects the first to third discharge paths to a second supply voltage in response to the clock signal. The first supply voltage is a power supply voltage, and the second supply voltage is a ground voltage.
In this embodiment, the precharge means optionally includes a first PMOS transistor that is coupled between the first supply voltage and the first node and is turned on/off according to the clock signal, and a second PMOS transistor that is coupled between the first supply voltage and the second node and is turned on/off according to the clock signal.
In this embodiment, the first switching means optionally includes an NMOS transistor having a current path formed between the first and third nodes and a gate connected to receive the input signal.
In this embodiment, the second switching means optionally includes an NMOS transistor having a current path formed between the second and third nodes and a gate coupled to the first node.
In this embodiment, the second precharge means optionally includes a PMOS transistor having a current path formed between the first supply voltage and the output terminal and a gate coupled to the second node.
In this embodiment, the third switching means optionally includes first and second NMOS transistors whose current paths are serially formed between the output terminal and the third node. Gates of the current paths are connected to the clock signal and the second node, respectively.
In this embodiment, the fourth switching means optionally includes an NMOS transistor having a current path formed between the third node and the second supply voltage and a gate coupled to receive the clock signal.
According to another aspect of the invention, a D flip-flop synchronized with a single clock signal to store an input signal includes a first input terminal, a second terminal for receiving a clock signal, an output terminal for outputting an output signal, a first power terminal for receiving a power supply voltage, and a second power terminal for receiving a ground voltage. A first charge supply means is coupled between the first power terminal and a first internal node and operates in synchronization with the clock signal. A second charge supply means is coupled between the first power terminal and a second internal node and operates in synchronization with the clock signal. A third charge supply means is coupled between the first power terminal and the output terminal and operates in synchronization with a potential of the second internal node. A first charge discharging means is coupled between the first and third internal nodes and operates in synchronization with the input signal. A second charge discharging means is coupled between the second and third internal nodes and operates in synchronization with a potential of the first internal node. A third charge discharging means is coupled between the output terminal and the third internal node and operates in synchronization with the clock signal. A charge discharging path supply means connects at least one of the first to third charge discharging means to the second power terminal.
According to still another aspect of the invention, a D flip-flop includes a first power terminal for receiving a power supply voltage, a second power terminal that receives a ground voltage, a first transistor, for example a MOS transistor, of a first conductive type that is coupled between the first power terminal and the first internal node and operates in synchronization with a clock signal, a second transistor of the first conductive type that is coupled between the first power terminal and the second internal node and operates in synchronization with the clock signal, a third transistor of the first conductive type that is coupled between the first power terminal and an output terminal and operates in response to a potential of the second internal node, a first transistor that is coupled between the first and third internal nodes and operates in response to an input signal, a second transistor of the second conductive type that is coupled between the second and third internal nodes and operates in synchronization with the potential of the first internal node, third and fourth transistors of the second conductive type that are serially coupled between the output terminal and the third internal node, a fifth transistor of the second conductive type that is coupled between the third internal node and the second power terminal and operates in response to the clock signal. The third transistor of the second conductive type operates in response to the clock signal, and the fourth transistor of the second conductive type operates in response to the potential of the second internal node.